The Lattice Semiconductor DDR Memory Controller IP Core provides a turnkey solution consisting of a controller, DDRPHY, and associated clocking and training logic to interface with DDR4 and LPDDR4 SDRAM. The IP Core is implemented in System Verilog HDL using the Lattice Radiant software integrated with the Synplify Pro synthesis tool. The Memory Controller simplifies the interfacing with external DDR4 and LPDDR4 memory for user applications.
LAV-AT-E30, LAV-AT-E70, LAV-AT-G70, LAV-AT-X70, LN2-CT-20