<?xml version="1.0"?>
<lsccip:ip version="1.0"
    xmlns:lsccip="http://www.latticesemi.com/XMLSchema/Radiant/ip"
    xmlns:xi="http://www.w3.org/2001/XInclude">

  <lsccip:general>
    <lsccip:vendor>latticesemi.com</lsccip:vendor>
    <lsccip:library>ip</lsccip:library>
    <lsccip:name>ddr_mc</lsccip:name>
    <lsccip:display_name>DDR Memory Controller</lsccip:display_name>
    <lsccip:version>2.8.0</lsccip:version>
    <lsccip:category>Processors_Controllers_and_Peripherals</lsccip:category>
    <lsccip:keywords>BusType_AXI4,BusType_APB</lsccip:keywords>
    <lsccip:type>cacheable</lsccip:type>
    <lsccip:min_radiant_version>2024.1</lsccip:min_radiant_version>
    <lsccip:min_esi_version>2024.1</lsccip:min_esi_version>
    <lsccip:supported_products>
      <lsccip:supported_family name="LATG1"></lsccip:supported_family>
      <lsccip:supported_family name="LAV-AT"></lsccip:supported_family>
	  <lsccip:supported_family name="LKH-CT"></lsccip:supported_family>
	  <lsccip:supported_family name="LKH-MH"></lsccip:supported_family>
	  <lsccip:supported_family name="LN2-CT"></lsccip:supported_family>
	  <lsccip:supported_family name="LN2-MH"></lsccip:supported_family>
      <lsccip:supported_family name="ap6a00"></lsccip:supported_family>
    </lsccip:supported_products>
    <lsccip:supported_platforms>
      <lsccip:supported_platform name="radiant"/>
      <lsccip:supported_platform name="esi" />
    </lsccip:supported_platforms>
  </lsccip:general>

  <xi:include href="settings.xml" parse="xml"/>
  <xi:include href="ports.xml" parse="xml"/>

  <lsccip:outFileConfigs>
    <lsccip:fileConfig name="wrapper" skip_uniquify="false" file_suffix="sv" file_description="top_level_system_verilog"></lsccip:fileConfig>
  </lsccip:outFileConfigs> 

  <xi:include href="bus_interface.xml" parse="xml" />
  <xi:include href="memory_map.xml" parse="xml" />

  <lsccip:componentGenerators>
    <lsccip:componentGenerator>
        <lsccip:name>select_ddr_protocol</lsccip:name>
        <lsccip:generatorExe>eval/select_protocol.py</lsccip:generatorExe>
    </lsccip:componentGenerator>
    <lsccip:componentGenerator>
        <lsccip:name>assign_pins</lsccip:name>
        <lsccip:generatorExe>eval/assign_pins.py</lsccip:generatorExe>
    </lsccip:componentGenerator>
  </lsccip:componentGenerators>

</lsccip:ip>
