The Lattice Semiconductor OpenLDI/FPD-LINK/LVDS Receiver Interface IP
converts a standard OpenLDI serial video interface into pixel clock
domain. The input interface for the design consists of a data bus,
vertical and horizontal sync flags, a data enable, and a clock in
OpenLDI (LVDS 7:1) interface format. Output interface consists of the
RGB control signals, pixel clock, up to four pixel data per pixel clock,
and debug signals.
LIFCL-40, LIFCL-33, LIFCL-17, LFD2NX-40, LFD2NX-17, LFCPNX-50, LFCPNX-100, LFMXO5-25, LFMXO5-55T, LFMXO5-100T, LAV-AT-E70, LAV-AT-G70, LAV-AT-X70
| 1.4.1 |
Added Radiant 2023.2 support. |
| 1.4.0 |
Added Avant device support. |
| 1.3.0 |
Integrated 1.2.1 updates to 1.3.0. Added LFMXO5 device support. |
| 1.2.1 | Updated generic PLL for Radiant 3.0. |
| 1.2.0 | Added CertusPro-NX support. |
| 1.1.0 |
Added support for JEIDA/VESA mode. Added support for LFCPNX device. |
| 1.0.1 | Testbench enhancement. |
| 1.0.0 | Initial release. |