latticesemi.com ip pcie_x4 PCIE_X4 4.0.1 Connectivity BusType_AHB-Lite,BusType_APB 3.1 2.1 SERIAL_IO_PADS SERIAL_IO_PADS Serial IO and PADS REFCLKP refclkp_i REFCLKN refclkn_i RXP0 link0_rxp_i RXN0 link0_rxn_i RXP1 link1_rxp_i RXN1 link1_rxn_i TXP0 link0_txp_o TXN0 link0_txn_o TXP1 link1_txp_o TXN1 link1_txn_o REFRET refret_i REXT rext_i CLK_RST_STATUS_0 CLK_RST_STATUS_0 Clock Reset and Status 0 AUX_CLK link0_aux_clk_i PERST_N link0_perst_n_i RST_USR_N link0_rst_usr_n_i AUX_POWER_DETECTED link0_user_aux_power_detected_i TRANSACTIONS_PENDING link0_user_transactions_pending_i FLR_ACK link0_flr_ack_i LTSSM_DISABLE link0_ltssm_disable_i CLKREQ_N link0_clkreq_n_io PCLK_OUT link0_clk_usr_o PL_LINK_UP link0_pl_link_up_o DL_LINK_UP link0_dl_link_up_o TL_LINK_UP link0_tl_link_up_o FLR link0_flr_o CLK_RST_STATUS_1 CLK_RST_STATUS_1 Clock Reset and Status 1 AUX_CLK link1_aux_clk_i PERST_N link1_perst_n_i RST_USR_N link1_rst_usr_n_i AUX_POWER_DETECTED link1_user_aux_power_detected_i TRANSACTIONS_PENDING link1_user_transactions_pending_i FLR_ACK link1_flr_ack_i LTSSM_DISABLE link1_ltssm_disable_i CLKREQ_N link1_clkreq_n_io PCLK_OUT link1_clk_usr_o PL_LINK_UP link1_pl_link_up_o DL_LINK_UP link1_dl_link_up_o TL_LINK_UP link1_tl_link_up_o FLR link1_flr_o PM_PORTS_0 PM_PORTS_0 Power Management Ports 0 PM_LTR_MSG_SEND link0_pm_ltr_msg_send_i PM_LTR_NOSNOOP_REQ link0_pm_ltr_nosnoop_req_i PM_LTR_SNOOP_REQ link0_pm_ltr_snoop_req_i PM_LTR_NOSNOOP link0_pm_ltr_nosnoop_i PM_LTR_SNOOP link0_pm_ltr_snoop_i PM_PB_DATA_REG_RD link0_pm_pb_data_reg_rd_i PM_PB_DATA_SEL link0_pm_pb_data_sel_o PM_DPA_STATUS link0_pm_dpa_status_i PM_DPA_CONTROL link0_pm_dpa_control_o PM_DPA_CONTROL_EN link0_pm_dpa_control_en_o PM_PORTS_1 PM_PORTS_1 Power Management Ports 1 PM_LTR_MSG_SEND link1_pm_ltr_msg_send_i PM_LTR_NOSNOOP_REQ link1_pm_ltr_nosnoop_req_i PM_LTR_SNOOP_REQ link1_pm_ltr_snoop_req_i PM_LTR_NOSNOOP link1_pm_ltr_nosnoop_i PM_LTR_SNOOP link1_pm_ltr_snoop_i PM_PB_DATA_REG_RD link1_pm_pb_data_reg_rd_i PM_PB_DATA_SEL link1_pm_pb_data_sel_o PM_DPA_STATUS link1_pm_dpa_status_i PM_DPA_CONTROL link1_pm_dpa_control_o PM_DPA_CONTROL_EN link1_pm_dpa_control_en_o DBG_TLP DBG_TLP TLP Debug Signals RX_READY dbg_link0_rx_ready_o RX_VALID dbg_link0_rx_valid_o TYPE dbg_link0_rx_sel_o DECODE dbg_link0_rx_cmd_data_o RX_SOP dbg_link0_rx_sop_o RX_DATA dbg_link0_rx_data_o RX_PARITY dbg_link0_rx_datap_o RX_EOP dbg_link0_rx_eop_o ECRC_ERR dbg_link0_rx_err_ecrc_o FUNCTION dbg_link0_rx_f_o TX_VALID dbg_link0_tx_valid_o TX_DATA dbg_link0_tx_data_o TX_PARITY dbg_link0_tx_datap_o TX_EOP dbg_link0_tx_eop_o NULLIFY dbg_link0_tx_eop_n_o TX_SOP dbg_link0_tx_sop_o TX_READY dbg_link0_tx_ready_o AXI_SOFT_BRIDGE_AXIMM_M AXI_SOFT_BRIDGE_AXIMM_M AXI-MM Interface for AXI_SOFT_BRIDGE AWADDR m0_aximm_awaddr_o AWPROT m0_aximm_awprot_o ARPROT m0_aximm_arprot_o ARQOS m0_aximm_arqos_o ARCACHE m0_aximm_arcache_o ARUSER m0_aximm_aruser_o ARLOCK m0_aximm_arlock_o AWVALID m0_aximm_awvalid_o WDATA m0_aximm_wdata_o WSTRB m0_aximm_wstrb_o WVALID m0_aximm_wvalid_o BREADY m0_aximm_bready_o ARADDR m0_aximm_araddr_o ARVALID m0_aximm_arvalid_o RREADY m0_aximm_rready_o AWID m0_aximm_awid_o AWLEN m0_aximm_awlen_o AWSIZE m0_aximm_awsize_o AWBURST m0_aximm_awburst_o AWLOCK m0_aximm_awlock_o AWCACHE m0_aximm_awcache_o AWREGION m0_aximm_awregion_o WLAST m0_aximm_wlast_o WUSER m0_aximm_wuser_o ARID m0_aximm_arid_o ARLEN m0_aximm_arlen_o ARSIZE m0_aximm_arsize_o ARBURST m0_aximm_arburst_o AWREADY m0_aximm_awready_i WREADY m0_aximm_wready_i BRESP m0_aximm_bresp_i BVALID m0_aximm_bvalid_i ARREADY m0_aximm_arready_i RDATA m0_aximm_rdata_i RRESP m0_aximm_rresp_i RVALID m0_aximm_rvalid_i RID m0_aximm_rid_i BID m0_aximm_bid_i RLAST m0_aximm_rlast_i AXI_SOFT_BRIDGE_AXILITE_M AXI_SOFT_BRIDGE_AXI-LITE_M AXI4-Lite Interface for AXI_SOFT_BRIDGE AWADDR m0_axil_awaddr_o AWPROT m0_axil_awprot_o ARPROT m0_axil_arprot_o AWVALID m0_axil_awvalid_o WDATA m0_axil_wdata_o WSTRB m0_axil_wstrb_o WVALID m0_axil_wvalid_o BREADY m0_axil_bready_o ARADDR m0_axil_araddr_o ARVALID m0_axil_arvalid_o RREADY m0_axil_rready_o AWREADY m0_axil_awready_i WREADY m0_axil_wready_i BRESP m0_axil_bresp_i BVALID m0_axil_bvalid_i ARREADY m0_axil_arready_i RDATA m0_axil_rdata_i RRESP m0_axil_rresp_i RVALID m0_axil_rvalid_i AXI_SOFT_DMA_M AXI_SOFT_DMA_M AXI-4 Memory Map Interface for DMA AWID m0_dma_axi_awid_o AWADDR m0_dma_axi_awaddr_o AWLEN m0_dma_axi_awlen_o AWSIZE m0_dma_axi_awsize_o AWBURST m0_dma_axi_awburst_o AWLOCK m0_dma_axi_awlock_o AWCACHE m0_dma_axi_awcache_o AWPROT m0_dma_axi_awprot_o AWVALID m0_dma_axi_awvalid_o AWREADY m0_dma_axi_awready_i WDATA m0_dma_axi_wdata_o WSTRB m0_dma_axi_wstrb_o WLAST m0_dma_axi_wlast_o WVALID m0_dma_axi_wvalid_o WREADY m0_dma_axi_wready_i BID m0_dma_axi_bid_i BVALID m_axi_s2mm_bvalid_i BRESP m0_dma_axi_bresp_i BVALID m0_dma_axi_bvalid_i BREADY m0_dma_axi_bready_o ARID m0_dma_axi_arid_o ARADDR m0_dma_axi_araddr_o ARLEN m0_dma_axi_arlen_o ARSIZE m0_dma_axi_arsize_o ARBURST m0_dma_axi_arburst_o ARLOCK m0_dma_axi_arlock_o ARCACHE m0_dma_axi_arcache_o ARPROT m0_dma_axi_arprot_o ARVALID m0_dma_axi_arvalid_o ARREADY m0_dma_axi_arready_i ARQOS m0_dma_axi_arqos_o ARUSER m0_dma_axi_aruser_o RID m0_dma_axi_rid_i RDATA m0_dma_axi_rdata_i RRESP m0_dma_axi_rresp_i RLAST m0_dma_axi_rlast_i RVALID m0_dma_axi_rvalid_i RREADY m0_dma_axi_rready_o AXIS_SOFT_DMA_S AXIS_SOFT_DMA_S AXI Stream Interface for DMA TREADY tx0_dma_axist_tready_o TVALID tx0_dma_axist_tvalid_i TDATA tx0_dma_axist_tdata_i TLAST tx0_dma_axist_tlast_i TREADY rx0_dma_axist_tready_i TVALID rx0_dma_axist_tvalid_o TDATA rx0_dma_axist_tdata_o TLAST rx0_dma_axist_tlast_o AHBL_DAT_SLV0 AHBL_DAT_SLV0 AHB-Lite slave 0 port HSELx s0_hsel_i HADDR s0_haddr_i HBURST s0_hburst_i HSIZE s0_hsize_i HMASTLOCK s0_hmastlock_i HPROT s0_hprot_i HTRANS s0_htrans_i HWDATA s0_hwdata_i HWRITE s0_hwrite_i HREADY s0_hreadyin_i HREADYOUT s0_hready_o HRESP s0_hresp_o HRDATA s0_hrdata_o AHBL_DAT_SLV1 AHBL_DAT_SLV1 AHB-Lite slave 1 port HSELx s1_hsel_i HADDR s1_haddr_i HBURST s1_hburst_i HSIZE s1_hsize_i HMASTLOCK s1_hmastlock_i HPROT s1_hprot_i HTRANS s1_htrans_i HWDATA s1_hwdata_i HWRITE s1_hwrite_i HREADY s1_hreadyin_i HREADYOUT s1_hready_o HRESP s1_hresp_o HRDATA s1_hrdata_o AHBL_CFG_SLV AHBL_CFG_SLV AHB-Lite slave port HSELx c_hsel_i HADDR c_haddr_i HBURST c_hburst_i HSIZE c_hsize_i HMASTLOCK c_hmastlock_i HPROT c_hprot_i HTRANS c_htrans_i HWDATA c_hwdata_i HWRITE c_hwrite_i HREADY c_hreadyin_i HREADYOUT c_hready_o HRESP c_hresp_o HRDATA c_hrdata_o AHBL_WDAT_MST0 AHBL_WDAT_MST0 AHB-Lite Wr master 0 port HADDR m0_w_haddr_o HBURST m0_w_hburst_o HSIZE m0_w_hsize_o HMASTLOCK m0_w_hmastlock_o HPROT m0_w_hprot_o HTRANS m0_w_htrans_o HWDATA m0_w_hwdata_o HWRITE m0_w_hwrite_o HREADY m0_w_hready_i HRESP m0_w_hresp_i HRDATA m0_w_hrdata_i AHBL_WDAT_MST1 AHBL_WDAT_MST1 AHB-Lite Wr master 1 port HADDR m1_w_haddr_o HBURST m1_w_hburst_o HSIZE m1_w_hsize_o HMASTLOCK m1_w_hmastlock_o HPROT m1_w_hprot_o HTRANS m1_w_htrans_o HWDATA m1_w_hwdata_o HWRITE m1_w_hwrite_o HREADY m1_w_hready_i HRESP m1_w_hresp_i HRDATA m1_w_hrdata_i AHBL_RDAT_MST0 AHBL_RDAT_MST0 AHB-Lite Rd master 0 port HADDR m0_r_haddr_o HBURST m0_r_hburst_o HSIZE m0_r_hsize_o HMASTLOCK m0_r_hmastlock_o HPROT m0_r_hprot_o HTRANS m0_r_htrans_o HWDATA m0_r_hwdata_o HWRITE m0_r_hwrite_o HREADY m0_r_hready_i HRESP m0_r_hresp_i HRDATA m0_r_hrdata_i AHBL_RDAT_MST1 AHBL_RDAT_MST1 AHB-Lite Rd master 1 port HADDR m1_r_haddr_o HBURST m1_r_hburst_o HSIZE m1_r_hsize_o HMASTLOCK m1_r_hmastlock_o HPROT m1_r_hprot_o HTRANS m1_r_htrans_o HWDATA m1_r_hwdata_o HWRITE m1_r_hwrite_o HREADY m1_r_hready_i HRESP m1_r_hresp_i HRDATA m1_r_hrdata_i APB_CFG_SLV APB_CFG_SLV APB slave port PSELx c_apb_psel_i PADDR c_apb_paddr_i PENABLE c_apb_penable_i PWDATA c_apb_pwdata_i PWRITE c_apb_pwrite_i PREADY c_apb_pready_o PSLVERR c_apb_pslverr_o PRDATA c_apb_prdata_o RX_TLP_0 RX_TLP_0 TLP receive 0 port READY link0_rx_ready_i VALID link0_rx_valid_o SOP link0_rx_sop_o EOP link0_rx_eop_o DATA link0_rx_data_o PARITY link0_rx_datap_o ECRC_ERR link0_rx_err_ecrc_o FUNCTION link0_rx_f_o TYPE link0_rx_sel_o DECODE link0_rx_cmd_data_o RX_TLP_1 RX_TLP_1 TLP receive 1 port READY link1_rx_ready_i VALID link1_rx_valid_o SOP link1_rx_sop_o EOP link1_rx_eop_o DATA link1_rx_data_o PARITY link1_rx_datap_o ECRC_ERR link1_rx_err_ecrc_o FUNCTION link1_rx_f_o TYPE link1_rx_sel_o DECODE link1_rx_cmd_data_o TX_TLP_0 TX_TLP_0 TLP transmit 0 port READY link0_tx_ready_o VALID link0_tx_valid_i SOP link0_tx_sop_i EOP link0_tx_eop_i NULLIFY link0_tx_eop_n_i DATA link0_tx_data_i PARITY link0_tx_datap_i TX_TLP_1 TX_TLP_1 TLP transmit 1 port READY link1_tx_ready_o VALID link1_tx_valid_i SOP link1_tx_sop_i EOP link1_tx_eop_i NULLIFY link1_tx_eop_n_i DATA link1_tx_data_i PARITY link1_tx_datap_i TLP_NP_CREDIT_0 TLP_NP_CREDIT_0 TLP NP credit 0 ports CREDIT_INIT link0_rx_credit_init_i CREDIT_NH link0_rx_credit_nh_i CREDIT_NH_INF link0_rx_credit_nh_inf_i CREDIT_RETURN link0_rx_credit_return_i CREDIT_INIT link0_tx_credit_init_o CREDIT_NH link0_tx_credit_nh_o CREDIT_RETURN link0_tx_credit_return_o TLP_NP_CREDIT_1 TLP_NP_CREDIT_1 TLP NP credit 1 ports CREDIT_INIT link1_rx_credit_init_i CREDIT_NH link1_rx_credit_nh_i CREDIT_NH_INF link1_rx_credit_nh_inf_i CREDIT_RETURN link1_rx_credit_return_i CREDIT_INIT link1_tx_credit_init_o CREDIT_NH link1_tx_credit_nh_o CREDIT_RETURN link1_tx_credit_return_o LMMI_SLV LMMI_SLV LMMI slave port CLK usr_lmmi_clk_i RSTN usr_lmmi_resetn_i REQUEST usr_lmmi_request_i OFFSET usr_lmmi_offset_i WRITE usr_lmmi_wr_rdn_i WDATA usr_lmmi_wdata_i RDATA usr_lmmi_rdata_o RD_VALID usr_lmmi_rdata_valid_o READY usr_lmmi_ready_o PCIE_CFG_REG PCIE_CFG_REG PCIe Config register port VALID ucfg_valid_i ADDR ucfg_addr_i FUNCTION ucfg_f_i BYTE_ENABLE ucfg_wr_be_i WRITE ucfg_wr_rd_n_i LINK ucfg_link_i WDATA ucfg_wr_data_i RDATA ucfg_rd_data_o RD_VALID ucfg_rd_done_o READY ucfg_ready_o AXI4STRM_RX_0 AXI4STRM_RX_0 AXI4 Stream Slave 0 port TREADY s0_tready_o TVALID s0_tvalid_i TLAST s0_tlast_i TDATA s0_tdata_i TSTRB s0_tstrb_i TKEEP s0_tkeep_i TID s0_tid_i TDEST s0_tdest_i AXI4STRM_RX_1 AXI4STRM_RX_1 AXI4 Stream Slave 1 port TREADY s1_tready_o TVALID s1_tvalid_i TLAST s1_tlast_i TDATA s1_tdata_i TSTRB s1_tstrb_i TKEEP s1_tkeep_i TID s1_tid_i TDEST s1_tdest_i AXI4STRM_TX_0 AXI4STRM_TX_0 AXI4 Stream Master 0 port TREADY m0_tready_i TVALID m0_tvalid_o TLAST m0_tlast_o TDATA m0_tdata_o TSTRB m0_tstrb_o TKEEP m0_tkeep_o TID m0_tid_o TDEST m0_tdest_o AXI4STRM_TX_1 AXI4STRM_TX_1 AXI4 Stream Master 1 port TREADY m1_tready_i TVALID m1_tvalid_o TLAST m1_tlast_o TDATA m1_tdata_o TSTRB m1_tstrb_o TKEEP m1_tkeep_o TID m1_tid_o TDEST m1_tdest_o INT_CRIT_0 INT_CRIT_0 Critical Interrupt Request 0 IRQ link0_int_critical_o INT_CRIT_1 INT_CRIT_1 Critical Interrupt Request 1 IRQ link1_int_critical_o INT_NORM_0 INT_NORM_0 Normal Interrupt Request 0 IRQ link0_int_normal_o INT_NORM_1 INT_NORM_1 Normal Interrupt Request 1 IRQ link1_int_normal_o pcie_addr_space_0 0x100000000 32 AHBL_DAT_SLV0_mem_map AHBL DAT SLV0 mem map AHBL_DAT_SLV0 0 524288 32 AHBL_DAT_SLV1_mem_map AHBL DAT SLV1 mem map AHBL_DAT_SLV1 0 524288 32 AHBL_CFG_SLV_mem_map AHBL CFG SLV mem map AHBL_CFG_SLV 0 524288 32 APB_CFG_SLV_mem_map APB CFG SLV mem map APB_CFG_SLV 0 524288 32