PCI Express for Avant

Description:

PCI Express® is a high performance, fully scalable, and well-defined standard for a wide variety of computing and communications platforms. As a packet-based serial technology, the PCI Express standard greatly reduces the number of required pins and simplifies board routing and manufacturing. PCI Express is a point-to-point technology, as opposed to the multi-drop bus in PCI. Each PCI Express device has the advantage of full duplex communication with its link partner to greatly increase overall system bandwidth. The basic data rate for a single lane is double that of the 32-bit/33 MHz PCI bus. A four-lane link has eight times the data rate in each direction of a conventional bus.
The Lattice PCIe x8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus. The Lattice PCIe x8 IP Core implementation is a hardened IP with soft logic provided for interface conversion options. The hardened IP is an integration of PHY and Link Layer blocks.
The Lattice PCIe x8 IP Core is supported in the Lattice Avant™-AT-G and Lattice Avant-AT-X FPGA device family and is available in the Lattice Radiant™ software.

Devices Supported:

Avant-AT-G, Avant-AT-X

References

Release Notes

2.1.0 IP Release Notes
2.0.0

PHY Configuration

  • Increased aggregation and bifurcation up to x8 lanes
  • Increased data rates of 8.0 Gbps, and 16.0 Gbps
  • Added 128b/130b encoding at 8 Gbps and 16 Gbps
  • Added support for PCIe L1-substate power management and Separate RefClk Independent SSC Architecture (SRIS)

Hard IP Link Layer Features

  • PCI Express Base Specification Revision 4.0 compliant including compliance with earlier PCI Express Specifications
  • Backward compatible with PCI Express 3.x, 2.x, 1.x
  • x8 PCI Express Lanes with support for bifurcation
  • Supported lane configurations:
    • 1 × 8, 1 × 4, 1 × 2, 1 × 1
1.1.0

PHY Configuration

  • Aggregation and bifurcation up to x4 lanes
  • Data rates of 2.5 Gbps, 5.0 Gbps
  • Selectable parallel data widths such as 8, 16, 32, 64
  • 8b/10b encoding at 2.5 Gbps and 5 Gbps
  • Adaptive and configurable RX Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalizer (DFE)
  • Adaptive and programmable TX equalization
  • Extensive PMA debug capability via read/write and read-only registers in PCS
  • Register-based control of all PCS-to-PMA signals
  • A wide range of reference clock frequencies with optional fractional frequency correction capability
  • A wide range of divided clock frequencies for external-to-PHY usage with optional spread-spectrum clock (SSC) capability
  • Built-in, on-chip SSC generation and full configuration from –5000 to +5000 ppm
  • Test support features such as near-end loopback, PLL bypass modes, and others
  • Protocol-compatible features such as LOS, squelch, power modes, and others

Hard IP Link Layer Features

  • PCI Express Base Specification Revision 2.0 compliant including compliance with earlier PCI Express Specifications
  • Backward compatible with PCI Express 1.x
  • x4 PCI Express Lanes with support for bifurcation
  • Supported lane configurations:
    • 1 × 4, 1 × 2, 1 × 1
1.0.1
  • Supports Synthesis/Timing/Simulation
  • Supports Gen1/2 x1/x2/x4 Endpoint
  • Supports AXI-L/LMMI for config bus
  • Supports AXI-S/TLP interface for data bus
  • Supports Example Design simulation using Questasim (refer to IPUG for details)
  • Supports up to 8 PF with workaround (refer to IPUG or ED. To be addressed in 2023.2 SP1)
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