# AXI Register Slice

## Description

The AXI Register Slice Core Connects one AXI Memory-Mapped Master to One AXI Memory-Mapped Slave Through a Set of Pipeline Registers, Typically to Break a Critical Timing Path. Features Supported:

- Individually Configurable for Each of The Five AXI Channels
- Supports AXI-3, AXI-4 and AXI4-Lite modes of AXI Protocol
- Supports three modes viz. Fully Weight, Light Weight and Input Registered Modes of Operation

## Devices Supported

LIFCL, LFD2NX, LFMXO5, LFCPNX, LAV-AT, LN2-CT, ECP5U, ECP5UM, ECP5UM5G, LatticeECP3

## References

- User Guide
- IP Release Notes