# CNN Plus Accelerator IP Core

## Description

The Lattice Semiconductor CNN Plus Accelerator IP Core is a calculation engine for Deep Neural Network with fix point weights. It calculates full layers of neural network including convolution layer, pooling layer, batch normalization layer and full connect layer by executing sequence code with weight values which is generated by the Lattice SensAI Neural Network Compiler tool. The engine is optimized for convolutional neural network, which is why it can be used for vision-based application such as classification or face detection and key phrase detection. The engine is not a simple accelerator which requires an extra processor; it can do all required calculations by itself.

Features:

- Selectable three implementation types:
  - Compact CNN
  - Optimized CNN
  - Extended CNN
- Selectable AXI4 or FIFO interface
- Support for convolution layer, max pooling layer, global average pooling layer, batch normalization layer, and full connect layer
- Configurable bit width of activation (16/8-bit)
- Configurable number of memory blocks for tradeoff between resource and performance
- Optimized for 3x3 2D convolution calculation
- Supports 2x2 max pooling
- Support for 2 x 2 max pooling/unpooling with max argument – Extended CNN only
- Supports global average pooling by full connect engine
- Configurable input byte mode: signed, unsigned and disable – only Compact CNN supports disable mode
- Partial DRAM access
- Configurable maximum burst length (32, 256) for AXI4 Interface
- Supports paired and quadruple convolution engines to improve performance – Optimized/Extended CNN only
- Configurable Line Buffer Size (512, 1024, 2048) - Optimized CNN only
- Supports general purpose output signal for controlling external logic via command code
- Added support for higher precision convolution calculation for improved overall result accuracy–Optimized/Extended CNN only.
- Significant improvement in Optimized engine utilization (Reduced LUTs, registers and EBRs) compared to v1.3.1 and earlier.
- Option for additional LUT reduction in Optimized Engine, with configurable reduction factor, by using DSP slices instead of LUTs.

## Devices Supported

LIFCL-40, LIFCL-33, LIFCL-33U, LIFCL-17, LFD2NX-40, LFD2NX-17, LFCPNX-50, LFCPNX-100

## References

- User Guide

## Revision History

1.4.0

- Added engine features listed above in green.
- Removed support for UT24C, UT24CP and LFMXO5 devices from this version onwards.

1.3.1 | Set Memory Type to SINGLE_RAM when selected device is LFMXO5-25.
1.3.0 | Added UT24C, UT24CP, and LFMXO5 device support.
1.2.2 | Fixed handling of small input size such as 2x2 and 1x1. Fixed blob storage support for byte address with word increase mode in writing operation.
1.2.1 | Fixed argmax index value at the last column of data. Removed "Dynamic support for various 1D convolution from 1 to 9 taps" from the list of features.
1.2.0 | Added LFCPNX support. Added Extended Machine Learning Type. Added OCTA mode for Compact CNN scratch pad. Added the following attributes: Convolution Engine, Scratch Pad Memory Mode, LRAM Enable Output Register and Maximum Argument Size.
1.1.1 | Fixed byte addressing in Compact CNN mode. Fixed DMA access issues.
1.1.0 | Added Embedded Mode option for selecting between AXI4 and FIFO interface. Added Use Paired Convolution Engine options for improving performance. Added General Purpose Output (gpo_o) signal. Added Line Buffer Size option for supporting VGA input. Added LFD2NX device support.
1.0.0 | Initial release.