# DDR3 SDRAM Controller

## Description

The Lattice Double Data Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) Controller
is a general-purpose memory controller that interfaces with industry standard DDR3
memory devices and modules compliant with the JESD-79.3 specification.

## Devices Supported

LIFCL-40, LIFCL-17, LFD2NX-40, LFD2NX-17, LFCPNX-100

## References

- User Guide

## Revision History

1.4.1

Fixed the missing activate issue when cmd_rdy_o are cmd_valid_i are changed from invalid to valid at the same time.
Added cmd_burst_cnt_i sweep in the testbench/testcase.vh.
Removed global clock constraint in the top_constraint.pdc and improve the constraints.
Synchronized the reset de-assertion inside the IP.
Added Enable External PLL Reset attribute.
Added external ports for write leveling start and done.
Added support for both internal and external refresh when Enable External PLL Reset and External Auto Refresh Port are selected.
Fixed precharge all command during internal auto refresh.

1.4.0

Updated read training logic based on validation in the board.
Added option to disable the internal PLL.
Updated the selectable values for Select Memory and RefClock attributes.
Changed the default value of Controller Reset to Memory attributes.
Updated the testbench to add write delay that would match with the PHY delay settings that worked on the board.
Fixed the cmd_burst_cnt_i=2 issue when 8:1 gearing ratio.

1.3.0 | Updated for Radiant 3.0.
1.2.1 | Updated PLL instance.
1.2.0 | Added LFCPNX support.
1.1.1 | Improved performance for 8:1 gearing ratio.
1.1.0 | Updated for Radiant 2.1. Added 8:1 gearing ratio support. Added eval folder. Added Certus-NX support. Updated clock signal names: clk_i, sclk_o. Updated PLL instance.
1.0.1 | Updated for Radiant 2.0 Service Pack 1.
1.0.0 | Preliminary release.