# CSI-2/DSI DPHY Rx

## Description

The Lattice Semiconductor D-PHY Rx IP converts DSI or CSI-2 data to 8-bit or
16-bit or 32-bit or 64-bit data for Lattice Semiconductor LIFCL family devices.
The CSI-2/DSI D-PHY Receiver Submodule IP is intended for use in applications
that require a D-PHY receiver in the FPGA logic.

## Devices Supported

LIFCL

## References

- User Guide

## Revision History

1.0.0 | Preliminary release.

## Limitations

- Gearing 16 option for Hard DPHY mode is supported in the GUI, but its functionality is not fully tested yet. We recommend users to use gearing 8 when data rate is 1.5 Gbps or under. To run data rate faster than 1.5 Gbps, please wait for the next release.

- CIL enabled option for Hard DPHY is available in the GUI, but its functionality is not fully tested yet. We recommend users to use CIL bypass mode until it is fully tested in the next release.

- Packet Formatter Off option is available in the GUI, but its functionality is not fully tested yet. We recommend users to use Packet Formatter ON option until it is fully tested in the next release. Users should be able to use Packet Formatter option ON along with the CSI-2/DSI D-PHY Transmitter IP with Packet Formatter option ON as well for pass-through type of bridging applications.

- AXI4-Stream interface option available in the GUI, but its functionality is not fully tested yet. We recommend users not to use AXI4-Stream interface until it is fully tested in the next release.

- Customer Test Bench current does not do any data checking. We recommend customers to add their data checking capability into the test bench themselves.