# CSI-2/DSI D-PHY Receiver

## Description

The Lattice Semiconductor D-PHY Receiver IP converts DSI or CSI-2 data to 8-bit or
16-bit or 32-bit or 64-bit data. The CSI-2/DSI D-PHY Receiver IP is intended
for use in applications that require a D-PHY receiver in the FPGA logic.

## Devices Supported

LIFCL-40, LIFCL-17, LFD2NX-40, LFD2NX-17

## References

- User Guide

## Revision History

1.1.1 | added deskew calibration support. adjusted Soft D-PHY HS-SETTLE parameter count. hid RX_FIFO parameters in the GUI when CIL is enabled.
1.1.0 | Added support for RX lane = 3 in the Verilog testbench. Fixed hs-settle timing for Soft D-PHY. Fixed ports when LMMI is enabled. Added support for LFD2NX.
1.0.1 | Production release.
1.0.0 | Initial release.