# CSI-2/DSI D-PHY Receiver

## Description

The Lattice Semiconductor D-PHY Receiver IP converts DSI or CSI-2 data to 8-bit or
16-bit or 32-bit or 64-bit data. The CSI-2/DSI D-PHY Receiver IP is intended
for use in applications that require a D-PHY receiver in the FPGA logic.

## Devices Supported

LIFCL-40, LIFCL-33, LIFCL-17, LFD2NX-40, LFD2NX-17, LFCPNX-50, LFCPNX-100, LFMXO5-25, LFMXO5-55T, LFMXO5-100T, LAV-AT-500E

## References

- User Guide

## Revision History

1.6.0 | Added Soft D-PHY delay cell settings in the GUI. Added support for CSI-2 Extended Virtual Channel ID. Added header ECC error check and correction. Added support for dynamic late rate reconfiguration (Hard D-PHY CIL-Enabled). Added support for LFMXO5-55T, LFMXO5-100T, and LAV-AT devices.
1.5.0 | Added support for LAV-AT-E devices.
1.4.3 | Removed partial encryption of dphy_rx_wrap module; no RTL source code change. Added checking of speed grade to determine the maximum supported data rate.
1.4.2 | Added more clear text portion in the partially encrypted RTL to resolve syntax error getting flagged when Reveal is disabled in v1.4.1; no RTL source code change. Added checking of package type to determine the maximum supported data rate.
1.4.1 | Unencrypted the hard D-PHY primitive instantiation to support Reveal insertion.
1.4.0 | Fixed clock constraints in the ldc file. Fixed VCS compilation errors: - Error-[IRIBS] Illegal range in bit-select - Error-[MEAFFS] No argument for format specification Added LFMXO5-25 support
1.3.0 | Fixed issue found in non-continuous clock mode (HS to LP transition detection)
1.2.0 | Added CertusPro-NX support.
1.1.2 | Updated INIT value of CLK_DESKEW_DLYCAL when data rate is less than or equal to 1.5 Gbps
1.1.1 | added deskew calibration support. adjusted Soft D-PHY HS-SETTLE parameter count. hid RX_FIFO parameters in the GUI when CIL is enabled.
1.1.0 | Added support for RX lane = 3 in the Verilog testbench. Fixed hs-settle timing for Soft D-PHY. Fixed ports when LMMI is enabled. Added Certus-NX support.
1.0.1 | Production release.
1.0.0 | Initial release.

## Limitation

This version does not currently support cases wherein word count (WC) is less than the corresponding data bus width (e.g. data bus width == 8 bytes, WC == 7). This will be fixed in the succeeding release.