# CSI-2/DSI D-PHY Transmitter

## Description

The Lattice Semiconductor D-PHY Tx IP converts 64-bit data to either DSI or
CSI-2 data for Lattice Semiconductor Crosslink-NX family devices.
The CSI-2/DSI D-PHY Transmitter Submodule IP is intended for use in
applications that require a D-PHY transmitter in the FPGA logic.

## Devices Supported

LIFCL-40, LIFCL-17, LFD2NX-40

## References

- User Guide

## Revision History

1.1.1 | Updated testbench for Radiant 2.2 compatibility
1.1.0 | Added support for ordinal data sequence (previously, input data must be lane interleaved). Testbench supports 3-lane configuration when packet formatter is disabled. Supports CIL-enabled configuration. Code enhancements to remove output glitches. External clock option provided for Hard D-PHY. Option for Soft PHY implementation Added support for LFD2NX.
1.0.1 | Update for SP1. | 1.0.0 | Initial release.