# CSI-2/DSI D-PHY Transmitter

## Description

The Lattice Semiconductor CSI-2/DSI D-PHY Transmitter IP Core converts data bytes from a requestor to either DSI or CSI-2 data format for the Lattice Avant™, Nexus™, and Nexus 2 platforms.The CSI-2/DSI D-PHY Transmitter Submodule IP is intended for applications that require a D-PHY transmitter in the FPGA logic. This IP supports both high-speed (HS) and low power (LP) modes. The payload data uses the high-speed mode whereas the control and status information are sent in low power mode. The number of D-PHY data lanes for data transmission is configurable. This IP supports 1, 2, 3, or 4 data lanes.

## Devices Supported

Crosslink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant, Certus-N2

## References

- User Guide

## Release Notes

2.2.0 | IP Release Notes
2.1.0 | Added Certus-N2 support.

2.0.0

Fixed functional bugs found in last release.
Added option to enable or disable Edge Clock Synchronizer and Divider blocks.
Enhanced constraint generation and implementation. Uses new IP constraint propagation method by SW.
Fixed issues with testbench.
Fixed issues related to internal LMMI signal initializations and access.
Corrected default setting of some of hard DPHY parameters.
Updated port list and names.
Other minor GUI fixes.

1.9.2 | Fixed minor bug in GUI.
1.9.1 | Added timing constraint .pdc automation.
1.9.0 | Fix for the data lane going to hs-0 before going to LP-11 during HS-TRAIL state. Fix for reduced LP00 and LP01 duration when t_LPX and t_HS_PREPARE is set to 2. Removed Hard D-PHY option in LIFCL-33U. Added support for Propel.
1.8.1 | Revised timing protocol parameter values. New GUI values reflect the behavior in simulation. Added a new clock port pll_clkos_i for Nexus Soft D-PHY for a more stable 90degree phase between clock and data lane. Added support for extended virtual ID. testbench not yet updated for this feature.
1.8.0 | Added support for Avant devices.
1.7.2 | Added checking of device, package and speed grade to determine the maximum line rate.
1.7.1 | Updated the testbench to match the IPUG and RTL AXI-4 stream mapping of wordcount and virtual channel ID.
1.7.0 | Added LFMXO5 support. Cleaned up data width warnings. Updated timing constraints.
1.6.0 | Revert synchronization of reset_n_i to byteclock domain (added in v1.5). Fixed VCS compilation error. Fixed AXI-4 mapping of packet fields.
1.5.0 | Fixed 1.2V offset on the clock N-channel when using the Soft PHY implementation. Synchronized reset_n_i in byteclock domain.
1.4.0 | Fixed Skew Calibration timing-related entries in GUI.
1.3.0 | Fixed counter bit width reset issue in TX Global Controller. Fixed Skew Calibration timing entries in GUI. Fixed LP RX issue in Soft D-PHY configuration. Fixed rounding error of reference clock in testbench.
1.2.0 | Added CertusPro-NX support.
1.1.5 | Fix for combinational loop in the skew calibration signals.
1.1.4 | Code enhancements to fix timing issues at data rates above 2000 Mbps. Captured updated GPLL module v1.2.2 with DIV_DEL parameter.
1.1.3 | DPHY packet enable bug fix. c2d_ready_o behaviour fix - assertion of this signal should wait for tinit_done_o. Initial deskew calibration timing fix.
1.1.2 | Added initial deskew calibration for data rates above 1.5 Gbps. Added support for optional periodic skew calibration. Changed the implementation of the DSI FIFO within the Packet Formatter module to EBR. Added the actual data rate and the deviation from the target data rate in the configuration window.
1.1.1 | Updated testbench for Radiant 2.2 compatibility.
1.1.0 | Added support for ordinal data sequence - Previous versions require input data to be lane interleaved. Testbench supports 3-lane configuration when packet formatter is disabled. Supports CIL-enabled configuration. Code enhancements to remove output glitches. External clock option provided for Hard D-PHY. Option for Soft PHY implementation Added Certus-NX support.
1.0.1 | Update for SP1.
1.0.0 | Initial release.

## Limitations

This section serves as a complement of the official User Guide.

2.2.0

Some configurations may fail Static Timing Analysis when compiling your design using LSE. If this happens,
consider compiling your design using the Synopsis Synplify Pro.
Some IP configurations may have slower Fmax when used in devices with slow speed grade. The following Fmax
values are approximates and may vary depending on the system-level design:

- Nexus devices: 110 MHz for Gear 8, 150 MHz for Gear 16
- Avant devices: 162 MHz

Escape Mode, Ultra Low Power State (ULPS), and Bus Turnaround sequences are not yet supported.
When CIL Bypass is unchecked, because of the limitation of the hard D-PHY IP when CIL is enabled, HS Sync-
Sequence for HS Skew Calibration is only 8 UI instead of 16 UI of all one.

2.1.0--

Some configurations may fail Static Timing Analysis when compiling your design using LSE. If this happens,
consider compiling your design using the Synopsis Synplify Pro.
Some IP configurations may have slower Fmax when used in devices with slow speed grade. The following Fmax
values are approximates and may vary depending on the system-level design:

- Nexus devices: 110 MHz for Gear 8, 150 MHz for Gear 16
- Avant devices: 162 MHz

Test Coverage Limitations:

- Configurations with Bypass Packet Formatter with Interleaved Input Data both checked are not yet tested.

Escape Mode, Ultra Low Power State (ULPS), and Bus Turnaround sequences are not yet supported.
When CIL Bypass is unchecked, because of the limitation of the hard D-PHY IP when CIL is enabled, HS Sync-
Sequence for HS Skew Calibration is only 8 UI instead of 16 UI of all one.

1.9.2-- | Escape Mode, Ultra Low Power State (ULPS), and Bus Turnaround sequences are not yet supported. When CIL Bypass is unchecked, because of the limitation of the hard D-PHY IP when CIL is enabled, HS Sync- Sequence for HS Skew Calibration is only 8 UI instead of 16 UI of all one.