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###      !!!READ ME PLEASE!!!								 ###
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## Eval file description
tb_top_eval.sv
 - Testbench of sample eval 
 
eval_top.sv
 - Top-level module of eval

eval.pdc
 - Design constraint of eval

## How to run Radiant Flow for eval (with Synplify Pro)
 - Add the eval top module 'eval/eval_top.sv' into 'Input Files'
 - Add the eval testbench  'eval/tb_top_eval.sv' into 'Input Files' for 'Simulation' only in 'Include for' option
 - Add the eval constraint 'eval/eval.pdc' into 'Post-Synthesis Constraint Files'
 - Run 'Synthesize Design' -> 'Map Design' -> 'Place & Route Design'

## How to run simulation for eval
 - 'Tools' -> 'Simulation Wizard' -> 'Next' with default options
 - In ModelSim, 'Simulate' -> 'Run' -> 'Run -All'

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## Versa file description (hardware version of eval)
tb_top_versa.sv
 - Testbench of sample versa 
 
versa_top.sv
 - Top-level module of versa

versa.pdc
 - Design constraint of versa

## How to run Radiant Flow for versa (with Synplify Pro)
 - Add the eval top module 'eval/versa_top.sv' into 'Input Files'
 - Add the eval testbench  'eval/tb_top_versa.sv' into 'Input Files' for 'Simulation' only, in the 'Include for' option
 - Add the eval constraint 'eval/versa.pdc' into 'Post-Synthesis Constraint Files'
 - Run 'Synthesize Design' -> 'Map Design' -> 'Place & Route Design' -> 'Export Files'
 - Do make sure LFG1156 package is selected (aligned with device used in Avant Versa board)

## How to run simulation for versa
 - 'Tools' -> 'Simulation Wizard' -> 'Next' with default options
 - In ModelSim, 'Simulate' -> 'Run' -> 'Run -All'
