# OpenLDI/FPD-LINK/LVDS Receiver

## Description

The Lattice Semiconductor OpenLDI/FPD-LINK/LVDS Receiver Interface IP
converts a standard OpenLDI serial video interface into pixel clock
domain. The input interface for the design consists of a data bus,
vertical and horizontal sync flags, a data enable, and a clock in
OpenLDI (LVDS 7:1) interface format. Output interface consists of the
RGB control signals, pixel clock, up to four pixel data per pixel clock,
and debug signals.

## Devices Supported

LIFCL-40, LIFCL-17, LFD2NX-40, LFD2NX-17, LFCPNX-100

## References

- User Guide

## Revision History

1.2.1 | Updated generic PLL for Radiant 3.0
1.2.0 | Added CertusPro-NX support.
1.1.0 | Added support for JEIDA/VESA mode. Added support for LFCPNX device.
1.0.1 | Testbench enhancement.
1.0.0 | Initial release.