For running a verilog simulation you need to do the following additional steps: 

1) Copy 'testbench' folder from ip directory into instance directory next to 'rtl' directory and .cfg file. 

2) Using Radiant tcl console go to newly created 'testbench' directory and run the command "source gen_def.tcl" to generate verilog defines file.

3) Run simulation wizard. You will notice that rtl top module is included into list already. 
    If you want to run a post synthesis simulation replace this file with 
    gate level verilog (named <<instanse_name>>_prim.v) that Radiant creates after synthesis.

4) Add all verilog files from testbench folder. 

5) Enjoy!