# I2C Target

## Description

The I2C Target IP provides a bridge between LMMI/APB interface and standard external I2C bus interface. It supports out-of-band interrupt and configurable transmit and receive FIFO to minimize intervention by the host. The following I2C features are supported:

- 7-bit and 10-bit Addressing Mode
- Different I2C bus speeds: Standard-mode, Fast-mode, Fast-mode Plus
- Clock stretching
- Integrated Pull-up
- Integrated Glitch filter

## Devices Supported

LIFCL-40, LIFCL-33, LIFCL-17, LFD2NX-40, LFD2NX-17, LFD2NX-9, LFD2NX-28, LFCPNX-50, LFCPNX-100, LFMXO5-25, LFMXO5-55T, LFMXO5-100T, UT24C40, UT24CP100, LAV-AT-E70, LAV-AT-G70, LAV-AT-X70, LN2-CT-20

## References

- User Guide

## Release Notes

2.3.0 | IP Release Notes
2.1.1 | Updated version of driver file.
2.1.0 | Added I2C SDA Register Depth attribute. Updated driver for register mapping and I2C Rx FIFO read.
2.0.0 | Updated terminologies to use Controller and Target
1.4.1 | Added driver version number, more comments, and removed magic numbers.
1.4.0 | Added Avant support.
1.3.0 | Modified metadata.xml to change minimum value of Tx/Rx_FIFO_Almost_Full/Empty_Flag to 1.
1.2.0 | Added LFMXO5 support.
1.1.0 | Added LFCPNX support.
1.0.3 | Reduced read latency by from 2 clock cycle to 1 clock cycle. Added Certus-NX support.
1.0.2 | Updated for Radiant 2.0 Service Pack 1.
1.0.1 | Initial release.
1.0.0 | Preliminary release.