# Memory Controller

## Description

The Lattice Semiconductor Memory controller Interface Module provides a solution to interface to DDR3 or LPDDR4 DDR Memory standards. Lattice provides a turnkey solution with controller, DDR PHY, the associated clocking scheme and training related logic.

Features:

- Memory Controller supports DDR3 (to be enabled in succeeding release) and LPDDR4, compliant to JESD79-3, JESD209-4 SDRAM standards
- Speeds of up to 533 MHz command or data speeds of 1066 MTps
- DDR widths of x8, x16, x32, and x64 for DDR3 and x16, x32, and x64 for LPDDR4
- Burst length for DDR3 is fixed BL8 and BL16/32 OTF for LPDDR4
- Command frequency: 200, 250, 300, 350, 400, and 533 MHz
- 8:1 (X4) gearing mode
- Configurable address widths to support various densities
- AHB-Lite interface support of single INCR4, WRAP4, and INCR8 for read transaction types
- AHB-Lite interface support of single INCR4 and INCR8 for write transaction types
- Periodic training support
  - Automatic programmable interval refresh
  - ZQ calibration
  - Temperature tracking for LPDDR4
  - Adaptive/derate refresh rate for extended temperature support LPDDR4
- Special features
  - Reliability support SEC DED ECC
  - Low power features DBI for LPDDR4
  - Automatic detection of idle triggering SREF entry
  - Dynamic On-Die Termination (ODT) controls
  - Polling and Out-of-band Interrupt support for error and extended temperature support
- Training and initialization support
  - Automatic SDRAM initialization
  - CA/VREF training for LPDDR4
  - Write leveling support
  - DQ-DQS skew optimization for Write training
  - Dynamic valid window optimization (Read and Write Path)

## Devices Supported

LFCPNX-100

## References

- User Guide

## Revision History

1.2.1 | Added limitation for DDR3. The DDR Interface Type GUI option has been fixed to LPDDR4.
1.2.0 | Updated for Radiant 3.1. Updated eval files to add the design for testing the IP on the board. Updated training logic to work on the board. Added Native I/F local data bus.
1.1.0 | Updated for Radiant 3.0. Added support for Micron WDQS Control Mode 2.
1.0.0 | Initial release.

## Limitation

The DDR3 mode is not yet enabled for the current release. It will be enabled in the succeeding release.