# PCIE_X1

## Description:

PCI Express® is a high performance, fully scalable, and well-defined standard for a wide variety of computing and communications platforms. As a packet-based serial technology, the PCI Express standard greatly reduces the number of required pins and simplifies board routing and manufacturing. PCI Express is a point-to-point technology, as opposed to the multi-drop bus in PCI. Each PCI Express device has the advantage of full duplex communication with its link partner to greatly increase overall system bandwidth. The basic data rate for a single lane is double that of the 32-bit/33 MHz PCI bus. A four-lane link has eight times the data rate in each direction of a conventional bus.
The Lattice PCIe x1 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus. The Lattice PCIe x1 IP Core implementation is a hardened IP with soft logic provided for interface conversion options. The hardened IP is an integration of PHY and Link Layer blocks.
The Lattice PCIe x1 IP Core is supported in the CrossLink™-NX, Certus™-NX and MachXO5T™-NX FPGA device families and is available in the Lattice Radiant™ software.

## Devices Supported:

Certus-NX (LFD2NX-28, LFD2NX-35, LFD2NX-65, LFD2NX-40), CrossLink-NX (LIFCL-40), MachXO5-NX (LFMXO5-35T, LFMXO5-65T), MachXO5-NX TD (LFMXO5-20TD, LFMXO5-30TD), MachXO5-NX TDQ (LFMXO5-20TDQ, LFMXO5-30TDQ)

## References

- IP Release Notes
- Lattice Avant and Nexus Linux PCIe Host Non-DMA Driver User Guide
- User Guide