# RISC-V MC CPU

## Description

RISC-V MC CPU with optional Cache, PIC and Timer

## Devices Supported

MachXO2, MachXO3, MachXO3D, LIFCL-40, LIFCL-17, LIFCL-33, LFD2NX-40, LFCPNX-100, LFMXO5-25

## References

- User Guide

## Revision History

2.3.0 | disable debug module for Avant performance enhancement fix vectored interrupt mode for cache cores simulation mode and debug mode cannot be selected together
2.2.2 | cache core optimization
2.2.1 | fix debug related issues for cache cores
2.2.0 | support LIFCL-33