# Scatter Gather Direct Memory Access Controller IP

## Description

The Scatter Gather Direct Memory Access Controller (SGDMAC) IP core provides access to the main memory independent of the processor. It offloads processor intervention. The processor initiates transfer to SGDMAC and receives an interrupt on completion of the transfer by the DMA Engine.
The Lattice SGDMAC IP core implements a configurable, AXI Lite-compliant DMA controller with scatter-gather capability. The directions for specifying the IP core configuration, including it in a user design, and directions for simulation and synthesis are provided in this user guide.

## Devices Supported

Certus-NX, Certus-N2, CrossLink-NX, CertusPro-NX, MachXO5-NX, Avant-E, Avant-G, Avant-X

## References

- User Guide
- SGDMA Driver API Reference

## Release Notes

2.3.0 | IP Release Notes

2.2.0

### Driver Updates

- Introduced new functions: mm2s_get_desc_complete_bit and s2mm_get_desc_complete_bit, enabling users to continuously poll for the descriptor's status.
- Within sgdma_instance_t, new variables have been added to allow independent configuration of MM2S and S2MM.

2.1.1 | Fixed protocol error on the AXI4-Lite interface that is used to access IP's Control and Status Registers.
2.1.0 | Fixed an issue with CDC-related SDC constraints being dropped. Added support for Lattice Certus-NX and Avant devices and for Questasim OEM Example Design Simulation.
2.0.1 | Fix an issue on AXI-S tlast and tvalid behaviour. Macros renamed and added external read/write apis.
2.0.0 | Rearchitect SGDMA, enabling AXI protocol. Not backward compatible to previous versions
1.2.0 | Added LFMXO5 support.
1.1.0 | Added LFCPNX support.
1.0.0 | Initial release.