####Constraining the IP
- The post-synthesis constraint file, constraint.pdc, is automatically generated in every IP generation
- Include eval/constraint.pdc in Post-synthesis Constraint Files before running STA
- There are clock paths that are constrained as asynchronous. 
  --- Heirarchy and wire names of these clocks might change (depending on the device and/or Radiant version), please update the .pdc file accordingly.
      --- Check the generated_clocks to get the accurate clock path/name of these clocks
