# SPI Controller

## Description

The SPI Controller IP provides a bridge between LMMI/AHB-Lite/APB interface and standard external SPI bus interface.

## Devices Supported

LIFCL-40, LIFCL-33, LIFCL-17, LFD2NX-40, LFD2NX-17, LFD2NX-9, LFD2NX-28, LFCPNX-50, LFCPNX-100, LFMXO5-25, LFMXO5-55T, LFMXO5-100T, UT24C40, UT24CP100, LAV-AT-E70, LAV-AT-G70, LAV-AT-X70, LN2-CT-20

## References

- User Guide

## Release Notes

2.3.0 | IP Release Notes
2.1.0 | Increased FIFO depth. Added Avant G/X support.
2.0.0 | Changed terminology to Controller.
1.4.2 | Added driver version number, more comments and non-blocking transfer mode.
1.4.1 | Updated to remove glitch in SS line when using SPI ENABLE register and Slave Select Pulse Mode = Non Pulse.
1.4.0 | Added Avant support.
1.3.1 | Added SPI Enable Register attribute (unchecked by default).
1.3.0 | Added IP driver and Propel 2.2 support. Added SPI Enable Register. Changed Clock Prescaler lower limit from 1 to 2.
1.2.0 | Added LFMXO5 support.
1.1.0 | Added LFCPNX support.
1.0.2 | Desired SCLK Frequency maximum value is now 'System Clock Frequency'/2. Reduced APB/AHB-Lite read latency from 2 to 1.
1.0.1 | Added LFD2NX support.
1.0.0 | Preliminary release.

## Limitation

The driver source code files are only compatible when SPI Enable Register attribute is unchecked.