# SPI Flash Controller

## Description

The Serial Peripheral Interface (SPI) flash controller provides an industry-standard interface between a central processing unit (CPU) and an off-chip SPI flash memory device.
The controller has two separate slave ports: Port S and Port C.
Port S can be used by the CPU to read from, or write to, any memory location within the SPI flash.
Port C provides a mechanism to configure the SPI flash and issue any command from the SPI Flash's command set.

## Devices Supported

LIFCL-40, LIFCL-33, LIFCL-17, LFD2NX-40, LFD2NX-17, LFCPNX-50, LFCPNX-100, LFMXO5-25, LFMXO5-55T, LFMXO5-100T, UT24C40, UT24CP100, LAV-AT-500E

## References

- User Guide

## Revision History

1.7.0 | Added status registers. Added "Flash Memory Map Size" IP GUI attribute. Updated testbench. Added status register checks in between transactions.
1.6.0 | Updated controller output for user-defined command registers. Removed option to set the sector size on the GUI.
1.5.0 | Updated controller output for status read register. Updated generated IP constraints. Added clock polarity and phase attribute setting and register.
1.4.0 | Added UT24C, UT24CP and LAV-AT support. Added AHB-L support for page buffer program and read.
1.3.1 | Separated memory mapping for AHB-L and APB in Propel.
1.3.0 | Added Propel support. Separated AHB-L and APB clock. Added "Data Port AHB Data Byte Endianness" and "First Transmitted Bit" attributes. Set "Control Port APB Address Width" attribute value to 11 only. Added support for 32-bit SPI Flash addressing. Improved user command registers. Added register for SCLK Rate attribute.
1.2.0 | Added LFMXO5 support. Removed option to enable/disbale Control Port. Enabled the Control Port always.
1.1.0 | Added CertusPro-NX support.
1.0.0 | Initial release.