# Unified Interconnect

## Description

The unified interconnect is a high-performance and low-latency interconnect fabric for AXI4 and AXI4-Lite, AHB-Lite or APB-based systems. Any AXI4 or AXI4-Lite, AHB-Lite or APB-compliant IP can be integrated into the system. The IP connects one or more memorymapped manager devices to one or more memory-mapped subordinate devices and supports optional clock domain crossing (CDC) between interfaces. Each manager can access different subordinates in parallel. When more than one initiator tries to reach the same target, access is arbitrated.

## Devices Supported

LIFCL, LFD2NX, LFMXO5, LFCPNX, LAV-AT, LN2-CT

## References

- User Guide
- IP Release Notes